The GPU Stack.

Thirteen layers. A handful of owners each.

The thing people call "the AI buildout" is really one supply chain stacked thirteen layers deep. Each layer takes the output of the one below and adds something only a few companies on earth know how to add. Miss any rung and the chip on top does not exist. Climb it once, top to bottom, then we will take each layer apart.

It starts as a rock.

Pull up the very bottom layer and you are holding quartz. Silicon dioxide, the second most common stuff in the Earth's crust. Ordinary sand is far too dirty for chips; the crucibles that hold molten silicon need quartz so pure it comes from essentially one valley: Spruce Pine, North Carolina. When Hurricane Helene flooded it in September 2024 and shut the mines for two weeks, the whole industry held its breath.

From there it is brute chemistry. Crush quartz with carbon in an arc furnace to get 99% metallurgical silicon, then run the Siemens process until you reach eleven nines: polysilicon so clean that stray atoms are measured in parts per trillion.

The deeper you dig, the more the map turns into a list of chokepoints. A chip is not just silicon. It needs a dozen elements that one country, sometimes one mine, happens to control.

Grow a perfect crystal. Slice it thin.

Melt that polysilicon at 1,425°C, dip in a single seed crystal, and pull it out slowly while it spins. Atoms lock onto the seed in flawless alignment and a cylindrical ingot grows, a metre or more of one continuous crystal. This is the Czochralski method, from 1915. Slice the ingot into 300mm discs, polish them mirror-flat to within a few atoms, and you have a wafer.

Five companies make essentially all of them. Two are Japanese, Shin-Etsu and SUMCO, and together they are about half the world. A blank 300mm wafer is the canvas. Everything above this line is printed onto it.

# A 300mm wafer is huge; a Blackwell-class die is also huge (~830 mm²).
import math
def dies_per_wafer(wafer_mm=300, die_mm2=830):
    r = wafer_mm / 2
    gross = math.pi * r**2 / die_mm2 \
          - math.pi * 2*r / math.sqrt(2*die_mm2)   # minus edge loss
    return int(gross)

def good_dies(gross, defects_cm2=0.1, die_mm2=830):
    y = math.exp(-defects_cm2 * die_mm2/100)        # Poisson yield model
    return int(gross * y)

g = dies_per_wafer()        # ~64 giant dies on the whole disc
good_dies(g)                # ~scarcity is physics, not just demand

To print atoms, you torture tin.

To draw features a few atoms wide you need light with a wavelength a few atoms wide. There is exactly one machine on Earth that does it, and exactly one company that makes it: ASML, in the Netherlands. An EUV scanner costs about $380M, weighs 150,000 kg, ships in 250 crates, and has 700,000+ parts from 5,000+ suppliers. ASML makes roughly 15% of them itself.

The light is the impossible part. 13.5nm light will not come from a lamp or an ordinary laser; no material even transmits it, so it can only be reflected, never focused through a lens. ASML makes it by abusing molten tin: fire a droplet into a vacuum, flatten it with one laser pulse, then vaporize it with a second, building a plasma four times hotter than the surface of the sun. Then do it 50,000 times a second.

# There is no EUV lightbulb. You make each photon by vaporizing tin.
for _ in every_second(50_000):              # 50k droplets/sec
    drop   = eject_tin(diameter_um=25, speed_ms=70)
    flatten(drop, laser="Nd:YAG")            # pre-pulse: sphere -> pancake
    plasma = zap(drop, laser="CO2", power_kW=30)  # -> 220,000°C
    euv    = plasma.emit(nm=13.5)             # only ~5% of the energy
    for m in optics:                       # ~10 mirror bounces, in vacuum
        euv = m.reflect(euv)                # ~70% survives each one
    wafer.expose(euv, through=reticle)      # one flash of the pattern

Two more chokepoints hide here. The light-sensitive photoresist is ~85% Japanese (JSR, Tokyo Ohka, Shin-Etsu). And ASML has never shipped a single EUV machine to China, by US and Dutch design, since 2019. This one layer is where the whole geopolitics of chips lives.

Build the chip up like a city.

A chip is not carved from a block. It is built up, layer by layer, like a city seen from above: lay down a film of material, print a pattern onto it, etch away everything you do not want, and repeat. A modern logic chip runs this cycle hundreds of times, across more than a thousand individual steps, in a cleanroom where a speck of dust is a catastrophe.

The company that runs this dance best is TSMC, which makes about 70% of the world's chips by foundry revenue and essentially all the leading-edge ones. It designs nothing of its own; it is a pure-play foundry. The cutting edge is now N2, where the transistor itself changes shape from a FinFET to a gate-all-around nanosheet.

Same math. Three philosophies.

So what is the finished chip actually doing? Almost all of modern AI is one operation, repeated trillions of times: take a stack of numbers, multiply it by a grid of numbers, add up the results. A matrix multiply. Training and running a neural network is mostly that.

A CPU is built for the opposite job: do one complicated thing fast, then the next. A few big clever cores. A GPU throws that out for thousands of small cores doing the same multiply in lockstep. A TPU or custom ASIC goes further, hard-wiring the multiply into a systolic array that does almost nothing else.

# The whole workload, basically:  Y = X @ W   (a matrix multiply)
def matmul_cpu(X, W):                 # a CPU walks the loops
    for i in range(X.rows):           # one core, one cell
        for j in range(W.cols):       # at a time
            Y[i][j] = dot(X.row(i), W.col(j))

# A GPU runs thousands of those dot-products at once.
# A TPU streams the whole matmul through a grid of wired cells.
#   one fat CPU core .......... 1x
#   thousands of GPU cores .... hundreds x
#   a systolic tensor array ... matmul as pure dataflow, no register churn

NVIDIA's lead is not only the silicon. It is CUDA, twenty years of software that every AI framework targets first. That moat is why hyperscalers build their own ASICs to escape it, and why almost none have, yet.

Feeding the beast. The memory wall.

A GPU that can do ten quadrillion operations a second is useless if you cannot feed it. The bottleneck in modern AI is usually not arithmetic, it is bandwidth: getting the model's billions of weights to the cores fast enough. This is the memory wall, and for inference, memory almost always loses.

The fix is HBM. Instead of a few memory chips across the board, you stack a dozen DRAM dies into a tower, drill thousands of vertical copper through-silicon vias straight down through them, and park the tower millimetres from the GPU. That buys you a bus thousands of bits wide and multiple terabytes per second.

# Generating each token means reading the whole model from memory.
def tokens_per_sec(params_B, bytes_each, hbm_TB_s):
    weight_bytes = params_B * 1e9 * bytes_each
    return hbm_TB_s * 1e12 / weight_bytes      # a hard ceiling

tokens_per_sec(70, 2, 3.35)   # 70B · FP16 · H100   -> ~24 tok/s
tokens_per_sec(70, 1, 8.0)    # 70B · FP8  · B200   -> ~114 tok/s
# Faster math can't help if you can't stream the weights. So: more HBM, more bandwidth.

Glue it together. This is the bottleneck.

Now you have a compute die and a stack of memory. They have to become one object. For decades, progress meant shrinking transistors; below ~3nm the real bottleneck moved here, to packaging: stitching multiple chiplets and HBM stacks onto a shared base so they talk at nearly on-chip speed. A single die can only be so big, the reticle limit is about 858 mm², so Blackwell is literally two dies fused into one.

TSMC's method is CoWoS: chip-on-wafer-on-substrate. The dies and HBM stacks sit on a silicon interposer, which sits on an ABF substrate, which sits on the board. CoWoS capacity literally caps how many H100s and B200s can exist: it is fully booked for 2026 with lead times over a year, and NVIDIA reportedly takes roughly 60% of it.

A delightful detail: that ABF insulating film is made by Ajinomoto, the Japanese company best known for inventing MSG. Their amino-acid chemistry happened to yield the perfect dielectric, so a seasoning company sits in the supply chain of every advanced chip. Final assembly and test that is not done in-house at TSMC goes to the OSATs.

When copper gives up, send light.

Now multiply the chip by a hundred thousand. A frontier cluster is not one GPU, it is a stadium of them that must behave like one machine, and here physics bites: an electrical signal at 800 gigabits a second dies after a metre or two of copper. Inside a rack, copper is fine. Between racks, you convert the data into light.

That is the job of the optical transceiver, the "light module." A tiny translator that takes electrical bits, imprints them onto a laser beam, fires them down a glass fiber, and turns them back into electrons at the far end. One big GPU needs around six of them, each burning ~30 watts, which is exactly why the industry is racing to move the optics onto the chip itself.

# 800G module = 8 lanes x 100G, light carried as PAM4 (4 levels/symbol)
def transmit(bits):                       # electrons -> photons
    lanes = dsp.encode_pam4(bits)            # retime, equalize, add FEC
    light = [laser[i].modulate(l) for i,l in enumerate(lanes)]
    return wdm.combine(light)               # many colors, one fiber

def receive(light):                       # photons -> electrons
    cur  = [photodiode.detect(c) for c in wdm.split(light)]
    volt = [tia.amplify(i) for i in cur]       # tiny current -> voltage
    return dsp.decode_pam4(volt)            # back to clean bits

The newest trick is co-packaged optics: build the laser engine in a CMOS fab (silicon photonics) and sit it right next to the switch die. NVIDIA's Quantum-X and Spectrum-X Photonics switches do this, dropping per-port power from ~30W toward ~9W, with the photonics built on TSMC's COUPE process. With the Rubin platform's Spectrum-6 Ethernet switch, CPO stops being a science project and ships as the default scale-out fabric.

Wire 72 GPUs into one brain.

The unit of compute is no longer a GPU; it is a rack. NVIDIA's GB200 NVL72 wires 72 Blackwell GPUs together with a copper NVLink spine and 9 NVSwitch trays so they behave like one giant accelerator: 130 terabytes per second of all-to-all bandwidth, 5,184 copper cables, one fridge-sized machine pulling ~120 kilowatts. Its successor, the Vera Rubin NVL72 (launched at CES 2026, at partners in H2 2026), doubles the spine to NVLink 6 at 260 TB/s.

Two networks, two jobs. Scale-up is inside the rack: NVLink, copper, lowest latency. Scale-out is between racks, over optics, where switch ASICs stitch tens of thousands of GPUs into one cluster. Broadcom owns >80% of that switch silicon; the racks themselves are bolted together by ODMs you half-know: Foxconn builds ~40% of GB200 racks, Quanta ~30%.

120 kilowatts. In one cabinet.

All of this eats power and spits heat. An NVL72 rack pulls about 120 kilowatts, roughly a hundred homes, through a single cabinet. Power arrives as AC, gets rectified, runs down a busbar, and is stepped down at the chip by VRMs. The industry is shifting from 48-volt to 800-volt DC distribution just to carry the current: the first small 800V deployments land in late 2026, aimed at NVIDIA's megawatt-class Kyber racks.

Air cooling is hopeless at this density, so the coolant touches the silicon: cold plates bolted onto each GPU, fluid pumped through a CDU, heat dumped to the building's water. This is why Vertiv became an AI stock, and why a quiet chip company, Monolithic Power, sits in the power path of nearly every GPU.

Follow the money to the top.

Climb out the top of the stack and you reach the people writing the cheques. Five hyperscalers, Amazon, Microsoft, Google, Meta, and Oracle, are on track to spend somewhere north of $700 billion on AI infrastructure in 2026 alone, and the guidance keeps getting revised up, not down. That is roughly four times what they spent the year GPT-4 launched.

Most of it flows to NVIDIA, who pays TSMC, who pays ASML and SK Hynix, all the way down. A new tier of neoclouds rents GPUs to whoever cannot get them. And at the very top sit the model labs, each commanding clusters of a million GPU-equivalents, turning all that silicon into the chatbot in your pocket.

The whole stack, on one page.

Here is everything we climbed, with the company that owns each rung and how concentrated it is. Read it top to bottom and the pattern is impossible to miss: almost every layer is a near-monopoly or a three-name club. The AI race is run on a supply chain with a dozen single points of failure.

So here is what the climb teaches. "The AI buildout" sounds like software. It is the most physical thing humans make: a rock from Appalachia, refined to eleven nines, printed by light made from exploding tin, stacked with memory, glued together by a seasoning company's film, lit up by lasers, and wired into a machine that draws the power of a small town.

Every rung is a near-monopoly. Whoever controls the narrowest one controls the pace of intelligence itself. Right now that is a Dutch company that makes a single impossible machine, and a Taiwanese company that runs it better than anyone alive. Learn their names before you learn the chatbots'.