The GPU Stack.

Thirteen layers, each owned by a handful of companies.

What people call "the AI buildout" is one supply chain, thirteen layers deep. Each layer takes what the layer below made and adds something that only a few companies in the world know how to add. If any layer is missing, the chip at the top cannot be made. Let's climb it once, from the sand at the bottom to the top, and then take each layer apart.

It starts as a rock.

At the very bottom of the stack is quartz: silicon dioxide, the second most common stuff in the Earth's crust. Ordinary sand is far too dirty for chips. The crucibles (the bowls that hold molten silicon) need quartz so pure that nearly all of it comes from one valley: Spruce Pine, North Carolina. When Hurricane Helene flooded the valley in September 2024 and shut the mines for two weeks, the whole industry watched nervously.

From there it is heavy chemistry. Heat quartz with carbon in an arc furnace, and the carbon pulls the oxygen away, leaving 99% pure metallurgical silicon. Then refine it with the Siemens process until it is 99.999999999% pure, which people call eleven nines. The result is polysilicon, so clean that stray atoms are counted in parts per trillion.

Look closer and you find more chokepoints: places where a single supplier could stop everything. Besides silicon, a chip needs a dozen other materials, and for many of them one country, sometimes one mine, controls most of the supply.

Grow a perfect crystal. Slice it thin.

Melt the polysilicon at 1,425°C, dip a small seed crystal into it, and pull the seed out slowly while it spins. As the silicon freezes onto the seed, its atoms line up with the seed's atoms, and a cylindrical ingot grows: a meter or more of one continuous crystal. This is the Czochralski method, from 1915. Slice the ingot into 300mm discs, polish them flat to within a few atoms, and you have a wafer.

Five companies make nearly all of the world's wafers. Two of them, Shin-Etsu and SUMCO, are Japanese, and together they make about half. Every layer from here up in the stack is printed onto this blank 300mm disc.

# A 300mm wafer is huge; a Blackwell-class die is also huge (~830 mm²).
import math
def dies_per_wafer(wafer_mm=300, die_mm2=830):
    r = wafer_mm / 2
    gross = math.pi * r**2 / die_mm2 \
          - math.pi * 2*r / math.sqrt(2*die_mm2)   # minus edge loss
    return int(gross)

def good_dies(gross, defects_cm2=0.1, die_mm2=830):
    y = math.exp(-defects_cm2 * die_mm2/100)        # Poisson yield model
    return int(gross * y)

g = dies_per_wafer()        # ~64 giant dies on the whole disc
good_dies(g)                # ~scarcity is physics, not just demand

The light that prints chips comes from exploding tin.

Light cannot draw a line much thinner than its own wavelength. So to draw features a few atoms wide, you need light with a wavelength only a few atoms wide. Only one kind of machine in the world can do this, and only one company makes it: ASML, in the Netherlands. An EUV scanner costs about $380M, weighs 150,000 kg, ships in 250 crates, and has 700,000+ parts from 5,000+ suppliers. ASML makes roughly 15% of those parts itself.

Making the light is the hardest part. No lamp or ordinary laser gives off 13.5nm light. No material lets it pass through, either, so it cannot be focused with a lens. It can only be bounced off mirrors. ASML makes the light from molten tin. A machine fires a droplet of tin into a vacuum, one laser pulse flattens it, and a second pulse vaporizes it into a plasma four times hotter than the surface of the sun. The hot tin gives off the light. This happens 50,000 times a second.

# There is no EUV lightbulb. You make each photon by vaporizing tin.
for _ in every_second(50_000):              # 50k droplets/sec
    drop   = eject_tin(diameter_um=25, speed_ms=70)
    flatten(drop, laser="Nd:YAG")            # pre-pulse: sphere -> pancake
    plasma = zap(drop, laser="CO2", power_kW=30)  # -> 220,000°C
    euv    = plasma.emit(nm=13.5)             # only ~5% of the energy
    for m in optics:                       # ~10 mirror bounces, in vacuum
        euv = m.reflect(euv)                # ~70% survives each one
    wafer.expose(euv, through=reticle)      # one flash of the pattern

This layer has two more chokepoints. About 85% of the light-sensitive photoresist comes from Japan (JSR, Tokyo Ohka, Shin-Etsu). And ASML has never shipped a single EUV machine to China, because the US and Dutch governments have blocked it since 2019. More of the political fight over chips happens at this layer than at any other.

A chip is built up one layer at a time.

The basic cycle has three steps: lay down a thin film of material, print a pattern onto it, and etch away the parts you do not want. Then repeat. A modern logic chip goes through this cycle hundreds of times, more than a thousand separate steps in all. It happens in a cleanroom, because a single speck of dust can ruin a chip.

The company that does this best is TSMC. It has about 70% of the world's foundry business, measured by revenue, and makes nearly all of the most advanced chips. It designs no chips of its own, which makes it a pure-play foundry. The newest process is N2, where the transistor itself changes shape, from a FinFET to a gate-all-around nanosheet.

CPUs, GPUs and TPUs do the same math in three different ways.

So what does the finished chip do? Almost all of modern AI is one operation, repeated trillions of times: take a stack of numbers, multiply it by a grid of numbers, and add up the results. This is called a matrix multiply. Training a neural network and running it are mostly this one operation.

A CPU is built for a different job: do one complicated thing quickly, then the next. It has a few big, clever cores. A GPU instead has thousands of small cores that all do the same multiply at the same moment, in lockstep. A TPU or other custom ASIC goes further. It builds the multiply directly into the circuit as a systolic array, and does almost nothing else.

# The whole workload, basically:  Y = X @ W   (a matrix multiply)
def matmul_cpu(X, W):                 # a CPU walks the loops
    for i in range(X.rows):           # one core, one cell
        for j in range(W.cols):       # at a time
            Y[i][j] = dot(X.row(i), W.col(j))

# A GPU runs thousands of those dot-products at once.
# A TPU streams the whole matmul through a grid of wired cells.
#   one fat CPU core .......... 1x
#   thousands of GPU cores .... hundreds x
#   a systolic tensor array ... matmul as pure dataflow, no register churn

NVIDIA's lead also comes from CUDA, twenty years of software that every AI framework supports first. That lock-in is why the biggest cloud companies build their own ASICs to get away from NVIDIA, and why almost none have managed it yet.

A fast GPU spends its time waiting on memory.

A GPU that can do ten quadrillion operations a second is useless if it cannot get numbers to work on fast enough. In modern AI the limit is usually bandwidth, not arithmetic: how fast the model's billions of weights can be moved from memory to the cores. This gap is called the memory wall. When a trained model is running and answering (inference), memory is almost always the slower side.

The fix is HBM. Instead of spreading a few memory chips around the circuit board, you stack a dozen DRAM dies into a tower. Thousands of vertical copper through-silicon vias run straight down through the stack, and the tower sits a few millimeters from the GPU. With so many short wires side by side, the connection is thousands of bits wide and moves multiple terabytes per second.

# Generating each token means reading the whole model from memory.
def tokens_per_sec(params_B, bytes_each, hbm_TB_s):
    weight_bytes = params_B * 1e9 * bytes_each
    return hbm_TB_s * 1e12 / weight_bytes      # a hard ceiling

tokens_per_sec(70, 2, 3.35)   # 70B · FP16 · H100   -> ~24 tok/s
tokens_per_sec(70, 1, 8.0)    # 70B · FP8  · B200   -> ~114 tok/s
# Faster math can't help if you can't stream the weights. So: more HBM, more bandwidth.

Joining the chips together is the bottleneck.

Now you have a compute die and a stack of memory. They have to be joined into one part. For decades, progress in chips meant shrinking transistors. Below ~3nm, the main bottleneck moved here, to packaging: mounting several chiplets and HBM stacks on a shared base so they can talk to each other almost as fast as if they were one chip. A single die can only be so big. The reticle limit, the largest area a scanner can print at once, is about 858 mm², so Blackwell is two dies joined into one package.

TSMC's method is CoWoS: chip-on-wafer-on-substrate. The dies and HBM stacks sit on a silicon interposer, which sits on an ABF substrate, which sits on the circuit board. The amount of CoWoS capacity sets a hard limit on how many H100s and B200s can be built. It is fully booked for 2026, customers wait over a year for it, and NVIDIA reportedly takes roughly 60% of it.

One odd detail: that ABF insulating film is made by Ajinomoto, the Japanese company best known for inventing MSG. Its amino-acid chemistry happened to produce an excellent electrical insulator, so a seasoning company is in the supply chain of every advanced chip. Final assembly and testing that TSMC does not do itself goes to outside contractors called OSATs.

Past a meter of copper, data travels as light.

Now multiply the chip by a hundred thousand. A cluster for training frontier models is a building full of GPUs that must behave like one machine, and here physics gets in the way: an electrical signal at 800 gigabits a second fades out after a meter or two of copper. Inside a rack, copper is fine. Between racks, you turn the data into light.

That is the job of the optical transceiver, often called a "light module." It takes electrical bits, encodes them onto a laser beam, sends the beam down a glass fiber, and turns the light back into electrical signals at the far end. One big GPU needs around six of them, each using ~30 watts. That power cost is why the industry is racing to move the optics onto the chip itself.

# 800G module = 8 lanes x 100G, light carried as PAM4 (4 levels/symbol)
def transmit(bits):                       # electrons -> photons
    lanes = dsp.encode_pam4(bits)            # retime, equalize, add FEC
    light = [laser[i].modulate(l) for i,l in enumerate(lanes)]
    return wdm.combine(light)               # many colors, one fiber

def receive(light):                       # photons -> electrons
    cur  = [photodiode.detect(c) for c in wdm.split(light)]
    volt = [tia.amplify(i) for i in cur]       # tiny current -> voltage
    return dsp.decode_pam4(volt)            # back to clean bits

The newest approach is co-packaged optics (CPO): build the laser engine in an ordinary CMOS chip fab (silicon photonics) and place it right next to the switch die. NVIDIA's Quantum-X and Spectrum-X Photonics switches do this. It cuts the power per port from ~30W toward ~9W, and the photonics are built on TSMC's COUPE process. With the Rubin platform's Spectrum-6 Ethernet switch, CPO stops being an experiment and ships as the default network that links racks together (scale-out).

Wire 72 GPUs together into one machine.

Today the basic unit of AI computing is a rack of GPUs. NVIDIA's GB200 NVL72 wires 72 Blackwell GPUs together with a copper NVLink spine and 9 NVSwitch trays, so they act like one giant accelerator. Every GPU can talk to every other one, with 130 terabytes per second of total bandwidth over 5,184 copper cables, in one fridge-sized machine that draws ~120 kilowatts. Its successor, the Vera Rubin NVL72 (launched at CES 2026, reaching partners in H2 2026), doubles the spine's speed with NVLink 6 at 260 TB/s.

There are two networks with two different jobs. Scale-up is the network inside the rack: NVLink over copper, with the lowest delay. Scale-out is the network between racks. It runs over optical fiber, and switch ASICs route the traffic that ties tens of thousands of GPUs into one cluster. Broadcom makes >80% of those switch chips. The racks themselves are assembled by contract manufacturers (ODMs) whose names you may half-know: Foxconn builds ~40% of GB200 racks, Quanta ~30%.

One cabinet draws 120 kilowatts.

All of this uses a lot of power and turns it into heat. An NVL72 rack draws about 120 kilowatts, as much as roughly a hundred homes, in a single cabinet. Power arrives as AC, is converted to DC, runs down a busbar, and is stepped down to low voltage at the chip by VRMs. The industry is moving from 48-volt to 800-volt DC distribution, because for the same power a higher voltage needs less current, and less current needs less copper. The first small 800V setups arrive in late 2026, built for NVIDIA's megawatt-class Kyber racks.

Air cannot carry away this much heat from so small a space, so liquid is brought right up to the chips. Metal cold plates are bolted onto each GPU, a CDU pumps fluid through them, and the heat goes into the building's water. This is why Vertiv became an AI stock. It is also why a little-known chip company, Monolithic Power, sits in the power path of nearly every GPU.

Follow the money to the top.

At the top of the stack are the companies paying for all of it. Five hyperscalers (Amazon, Microsoft, Google, Meta, and Oracle) are on track to spend more than $700 billion on AI infrastructure in 2026 alone, and their forecasts keep going up. That is roughly four times what they spent the year GPT-4 launched.

Most of that money goes to NVIDIA, which pays TSMC, which pays ASML and SK Hynix, and so on down the stack. A newer group of companies, the neoclouds, rents GPUs to anyone who cannot get enough elsewhere. At the very top are the model labs. Each one runs clusters of a million GPU-equivalents and turns all that silicon into the chatbot on your phone.

The whole stack, on one page.

Here is every layer we climbed, with the companies that own it and how concentrated it is. Read it top to bottom and the pattern is clear: almost every layer is controlled by one company, or by two or three. The AI race runs on a supply chain with a dozen single points of failure, places where trouble at one company could stall everything above it.

"The AI buildout" sounds like a software story. It is the most physical thing humans make: a rock from Appalachia, refined to eleven nines, printed by light made from exploding tin, stacked with memory, joined together on a seasoning company's film, linked by lasers, and wired into a machine that draws the power of a small town.

Almost every layer is a near-monopoly. Whoever controls the narrowest one controls how fast AI can advance. Right now those are ASML, the Dutch company that makes the only EUV machines, and TSMC, the Taiwanese company that uses them better than anyone. Learn their names before you learn the chatbots'.